Experience Summary
• 3+ years of experience in digital ASIC/VLSI design, verification, silicon implementation and probe-station testing in mixed-signal team with 4 successful tapeouts using custom designed low voltage and low power cell library
• 3+ years of experience in RTL design & logic synthesis, timing constrain creation, analysis and optimization, ASIC physical design including floor planning, power planning/routing, CTS, place/route, static timing analysis & signal integrity check, formal verification/logic equivalence check, ECOs and DRC & LVS
• Expertise in Energy-Efficient Standard Cell Library/IP development, transistor/schematic level designing/tuning for performance
• Extensive experience in Verilog/VHDL, Unix, Tcl, Objective-C, C/C++/Java, Matlab, PCB Design and lab bring-up
• Familiar with SRAM, computer architecture, micro-architecture, communication, arithmetic datapath and analog design
• Demonstrated spoken/written communication skills, team player, self-driven, detail-oriented and believer of fast delivery